用xilinx ISE14.2进行综合时报这个错误,该怎么改?INTERNAL_ERROR:Xst:cmain.c:3423:1.29 - Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support. 有

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用xilinx ISE14.2进行综合时报这个错误,该怎么改?INTERNAL_ERROR:Xst:cmain.c:3423:1.29 - Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support. 有
用xilinx ISE14.2进行综合时报这个错误,该怎么改?
INTERNAL_ERROR:Xst:cmain.c:3423:1.29 - Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support.
有这个错误时候,仿真的波形图可以出来,但是view RTL Schematic 看不了,
当我换了台机器,进行综合时,没有这个错误了,又出现：ERROR:Pack:2309 - Too many bonded comps of type "IOB" found to fit this device.
ERROR:Map:237 - The design is too large to fit the device. Please check the Design Summary section to see which resource requirement for your design exceeds the resources available in the device. Note that the number of slices reported may not be reflected accurately as their packing might not have been completed. 这两个错误,这个时候就无法进行仿真了.
然后我又把两个模块单独进行综合,结果一个模块报出第一个错误,第二个模块报出第二个错误.
关于第二个错误说我IO单元太多,但是我的代码中IO单元不多啊.
求大神速救!
谢谢!

用xilinx ISE14.2进行综合时报这个错误,该怎么改?INTERNAL_ERROR:Xst:cmain.c:3423:1.29 - Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support. 有
第一个错误就是因为你的电脑的主板有问题,我当时用的是华硕的主板,后来换了微星的主板就好了,第二个问题就是你所使用的资源和IO太多了但是你所选择的FPGA型号却没有这么多资源

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